论文信息 - High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology

High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology

Random variation of threshold voltage (Vt) in MOSFETs plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt variation requires a large volume of measurements of minimum size devices to understand the high sigma behavior. At the same time, a rapid measurement approach is required to keep the total measurement time practical. Here we describe a new test structure and measurement approach that enables practical characterization of Vt distributions to high sigma and its application to 14nm Logic FinFET technology. We show that both NMOS and PMOS single fin devices have very low random Vt variation of 19mV and 24mV respectively, normally distributed out to +/-5σ.

[1] M. D. Giles,et al. Process Technology Variation , 2011, IEEE Transactions on Electron Devices.

[2] T. Hiramoto,et al. Analysis of NMOS and PMOS Difference in $V_{T}$ Variation With Large-Scale DMA-TEG , 2009, IEEE Transactions on Electron Devices.

[3] Mark Y. Liu,et al. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[4] C. Auth,et al. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[5] R. Chau,et al. A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.