A Learning Multiple-Valued Logic Network that can Explain Reasoning (特集 学習と自己組織化のアルゴリズム--理論とその応用)

[1]  Emil L. Post Introduction to a General Theory of Elementary Propositions , 1921 .

[2]  Yutaka Hata,et al.  Gate model networks for minimization of multiple-valued logic functions , 1993, [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic.

[3]  M. Yoeli,et al.  Logical Design of Ternary Switching Circuits , 1965, IEEE Trans. Electron. Comput..

[4]  Michitaka Kameyama,et al.  Design and implementation of quaternary NMOS integrated circuits for pipelined image processing , 1987 .

[5]  Masayuki Matsumoto,et al.  Layered MVL neural networks capable of recognizing translated characters , 1992, [1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic.

[6]  Hiroki Matsumoto,et al.  Algebraic properties of a learning multiple-valued logic network , 1993, [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic.

[7]  Stephen Y. H. Su,et al.  The Relationship Between Multivalued Switching Algebra and Boolean Algebra Under Different Definitions of Complement , 1972, IEEE Transactions on Computers.

[8]  Hamid R. Berenji,et al.  Learning and tuning fuzzy logic controllers through reinforcements , 1992, IEEE Trans. Neural Networks.

[9]  Zheng Tang,et al.  A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications , 1998, IEEE Trans. Computers.

[10]  Hiroki Matsumoto,et al.  Algorithm and implementation of a learning multiple-valued logic network , 1993, [1993] Proceedings of the Twenty-Third International Symposium on Multiple-Valued Logic.

[11]  Donald D. Givone,et al.  A Minimization Technique for Multiple-Valued Logic Systems , 1968, IEEE Transactions on Computers.

[12]  Masayuki Matsumoto,et al.  A design of multiple-valued logic neuron , 1990, Proceedings of the Twentieth International Symposium on Multiple-Valued Logic.