On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST

In the context of analog BIST for A-to-D converters, this paper presents an implementation of an on-chip ramp generator. It is demonstrated that the proposed original adaptive scheme allows the internal generation of a highly saw-tooth signal with a very precise control of the signal amplitude. In addition, the implementation of the adaptive ramp generator exhibits a very low silicon area.

[1]  Gordon W. Roberts,et al.  Arbitrary-precision signal generation for bandlimited mixed-signal testing , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[2]  Narumi Sakashita,et al.  A built-in self-test for ADC and DAC in a single-chip speech CODEC , 1993, Proceedings of IEEE International Test Conference - (ITC).

[3]  Gordon W. Roberts,et al.  A BIST scheme for a SNR, gain tracking, and frequency response test of a sigma-delta ADC , 1995 .

[4]  Florence Azaïs,et al.  A low-cost adaptive ramp generator for analog BIST applications , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[5]  Gordon W. Roberts,et al.  An analog multi-tone signal generator for built-in-self-test applications , 1994, Proceedings., International Test Conference.

[6]  Taco Zwemstra,et al.  Built-in self-test methodology for A/D converters , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[7]  Karim Arabi,et al.  Efficient and accurate testing of analog-to-digital converters using oscillation-test method , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[8]  Florence Azaïs,et al.  Hardware resource minimization for histogram-based ADC BIST , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[9]  Edgar Sánchez-Sinencio,et al.  Auto-calibrating analog timer for on-chip testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[10]  Abhijit Chatterjee,et al.  A signature analyzer for analog and mixed-signal circuits , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[11]  Michel Renovell,et al.  Towards an ADC BIST scheme using the histogram test technique , 2000, Proceedings IEEE European Test Workshop.

[12]  Stephen K. Sunter,et al.  A simplified polynomial-fitting algorithm for DAC and ADC BIST , 1997, Proceedings International Test Conference 1997.

[13]  Gordon W. Roberts,et al.  Analog Signal Generation for Built-In-Self-Test of Mixed-Signal Integrated Circuits , 1995 .