Modeling and validation of pipeline specifications

Verification is one of the most complex and expensive tasks in the current Systems-on-Chip design process. Many existing approaches employ a bottom-up approach to pipeline validation, where the functionality of an existing pipelined processor is, in essence, reverse-engineered from its RT-level implementation. Our validation technique is complementary to these bottom-up approaches. Our approach leverages the system architect's knowledge about the behavior of the pipelined architecture, through architecture description language (ADL) constructs, and thus allows a powerful top-down approach to pipeline validation. The most important requirement in top-down validation process is to ensure that the specification (reference model) is golden. This paper addresses automatic validation of processor, memory, and coprocessor pipelines described in an ADL. We present a graph-based modeling that captures both structure and behavior of the architecture. Based on this model, we present algorithms to ensure that the static behavior of the pipeline is well formed by analyzing the structural aspects of the specification. We applied our methodology to verify specification of several realistic architectures from different architectural domains to demonstrate the usefulness of our approach.

[1]  Gert Goossens,et al.  Chess: retargetable code generation for embedded DSP processors , 1994, Code Generation for Embedded Processors.

[2]  Rajat Moona,et al.  Processor modeling for hardware software codesign , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[3]  Nikil D. Dutt,et al.  Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models , 2003, 14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings..

[4]  Kunle Olukotun,et al.  Verifying correct pipeline implementation for microprocessors , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[5]  Nikil D. Dutt,et al.  Automatic verification of in-order execution in microprocessors with fragmented pipelines and multicycle functional units , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Pierre G. Paulin,et al.  Flexware: A flexible firmware development environment for embedded systems , 1994, Code Generation for Embedded Processors.

[7]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[8]  David L. Dill,et al.  Automatic verification of Pipelined Microprocessor Control , 1994, CAV.

[9]  Srinivas Devadas,et al.  ISDL: an instruction set description language for retargetability , 1997, DAC.

[10]  Eko Fajar Nurprasetyo,et al.  A Programming Language for Processor Based Embedded Systems , 1998 .

[11]  Rainer Leupers,et al.  Retargetable Code Generation Based on Structural Processor Description , 1998, Des. Autom. Embed. Syst..

[12]  David L. Dill,et al.  Formal Verification of Out-of-Order Execution Using Incremental Flushing , 1998, CAV.

[13]  Heinrich Meyr,et al.  LISA-machine description language and generic machine model for HW/SW co-design , 1996, VLSI Signal Processing, IX.

[14]  Randal E. Bryant,et al.  Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction , 2000, Proceedings 37th Design Automation Conference.

[15]  Heinrich Meyr,et al.  Architecture implementation using the machine description language LISA , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[16]  David Cyrluk,et al.  Microprocessor Verification in PVS - A Methodology and Simple Example , 1993 .

[17]  Kunle Olukotun,et al.  Verifying correct pipeline implementation for microprocessors , 1997, ICCAD 1997.

[18]  Nikil D. Dutt,et al.  EXPRESSION: a language for architecture exploration through compiler/simulator retargetability , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[19]  Edmund M. Clarke,et al.  Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking , 1996, FMCAD.

[20]  Nikil D. Dutt,et al.  Processor-memory co-exploration driven by a Memory-Aware Architecture Description Language , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[21]  Michel Dubois,et al.  Verification techniques for cache coherence protocols , 1997, CSUR.

[22]  Rainer Leupers,et al.  Retargetable generation of code selectors from HDL processor models , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[23]  Mark Bickford,et al.  Formal verification of a pipelined microprocessor , 1990, IEEE Software.

[24]  Miroslav N. Velev,et al.  Formal Verification of VLIW Microprocessors with Speculative Execution , 2000, CAV.

[25]  Nikil D. Dutt,et al.  Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions , 2002, DIPES.

[26]  Jun Sawada,et al.  Processor Verification with Precise Exeptions and Speculative Execution , 1998, CAV.

[27]  David Van Campenhout,et al.  Specification and verification of pipelining in the ARM2 RISC microprocessor , 1998, TODE.

[28]  Adrian J. Isles,et al.  Formal verification of pipeline control using controlled token nets and abstract interpretation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[29]  Ganesh Gopalakrishnan,et al.  Systematic verification of pipelined microprocessors , 2000 .

[30]  Christian Jacobi.  Formal Verification of Complex Out-of-Order Pipelines by Combining Model-Checking and Theorem-Proving , 2002, CAV.

[31]  Maria Freericks,et al.  The nml machine description formalism , 1991 .

[32]  Ranjit Jhala,et al.  Microarchitecture Verification by Compositional Model Checking , 2001, CAV.

[33]  Jun Sawada,et al.  Trace Table Based Approach for Pipeline Microprocessor Verification , 1997, CAV.

[34]  Chuck Siska,et al.  A processor description language supporting retargetable multi-pipeline DSP program development tools , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).

[35]  Mark Aagaard,et al.  A Framework for Microprocessor Correctness Statements , 2001, CHARME.

[36]  Nikil Dutt,et al.  Architecture Description Language driven Validation of Processor , Memory , and Co-Processor Pipelines , .