Design of Arbiters and Allocators Based on Multi-Terminal BDDs

Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways, from hardware to firmware to software. The paper presents a new computer-aided technique that can produce representations of arbiters/allocators in a form of a Multi-Terminal Binary Decision Diagram (MTBDD) with close to minimum cost and width. This diagram can then serve as a prototype for a cascade of multiple-output look-up tables (LUTs) that implements the given function, or for efficient firmware implementation. The technique makes use of iterative decomposition of integer functions of Boolean variables and a variable-ordering heuristic to order variables. The LUT cascades lead directly to the pipelined design, simplify wiring and testing and can compete with the traditional FPGA design in performance and with PLA design in chip area.

[1]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[2]  Shinobu Nagayama,et al.  Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams , 2005, J. Multiple Valued Log. Soft Comput..

[3]  Shinobu Nagayama,et al.  Numerical Function Generators Using LUT Cascades , 2007, IEEE Transactions on Computers.

[4]  Michael Yoeli.  The Synthesis of Multivalued Cellular Cascades , 1970, IEEE Transactions on Computers.

[5]  Václav Dvorák.  Bounds on Size of Decision Diagrams , 1997, J. Univers. Comput. Sci..

[6]  Rolf Drechsler,et al.  Binary Decision Diagrams - Theory and Implementation , 1998 .

[7]  Václav Dvorák.  Efficient Evaluation of Multiple-Output Boolean Functions in Embedded Software or Firmware , 2007, J. Softw..

[8]  Tsutomu Sasao,et al.  On LUT cascade realizations of FIR filters , 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

[9]  Tsutomu Sasao,et al.  BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades , 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[10]  Tsutomu Sasao.  Radix converters: complexity and implementation by LUT cascades , 2005, 35th International Symposium on Multiple-Valued Logic (ISMVL'05).

[11]  Tsutomu Sasao,et al.  Implementation of Multiple-Valued CAM Functions by LUT Cascades , 2006, 36th International Symposium on Multiple-Valued Logic (ISMVL'06).

[12]  Randal E. Bryant,et al.  On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.

[13]  鈴木 一正.  COOL Chips VIII : IEEE Symposium on Low-Power and High-Speed Chips , 2005 .

[14]  Tadeusz Luba,et al.  Decomposition of Boolean Functions Specified by Cubes , 2003, J. Multiple Valued Log. Soft Comput..

[15]  Tsutomu SASAO,et al.  Programmable Logic Device with an 8-stage cascade of 64 K-bit Asynchronous SRAMs , 2005 .

[16]  Tsutomu Sasao,et al.  Design of Address Generators Using Multiple LUT Cascade on FPGA , 2006 .