The Design and Implementation of a Highly Efficient Motion Estimation Engine for HEVC Systems

This paper presents the algorithm and VLSI architecture of a highly efficient Motion Estimation (ME) for High Efficiency Video Coding (HEVC) systems. To be specific, this paper proposes an Adaptive Fast Search Algorithm where the search space is adaptive to the characteristics of the video and the number of search candidates is greatly reduced. The experimental results show that, compared to the conventional approaches, this algorithm reduces the computational complexity by 54% with a marginal 2.01% performance degradation. Furthermore, the VLSI architecture and circuit implementation of the proposed ME engine is presented in this paper. The architectural and circuit-level optimizations for enhancing the throughput and reducing the complexity are illustrated. The proposed ME system is underwent the ASIC design flow and realized based on the Xilinx Zynq UltraScale+ FPGA platform. The results show that the, for ASIC and FPGA, the implemented ME achieves 60 frames per second (fps) and 30 fps with resolution of 3840×2160 respectively. The efficiency is also significantly enhanced.