A monolithic LTE interleaver generator for highly parallel SMAP decoders

The LTE standard specifies a throughput of 150MBit/s, while the upcoming true 4G LTE Advanced standard will push this throughput to 1 GBit/s. To achieve this throughput while fulfilling the low power requirements of mobile devices, future receiver circuit architectures need to deploy a high internal parallelism. The LTE standard has been designed with this parallelism in mind, using a QPP interleaver inside the turbo code decoder. In this paper we present a novel method to implement the QPP interleaver which significantly reduces power and area of this circuit.

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