High-performance VLSI multiplier with a new redundant binary coding

This paper describes the design of a 16×16 redundant binary multiplier for signed 2's complement numbers. The multiplier uses a new coding scheme for representing radix-2 signed digits. The coding results in a factor of two reduction in the number of summands used with respect to the modified Booth algorithm. The design has a small number of modular cells and regular routing, making it suitable for automatic synthesis of larger data-width multipliers. In addition, the row-based redundant binary adder tree is an ideal structure for high-throughput applications.

[1]  Robert O. Winder,et al.  Majority Gate Networks , 1964, IEEE Trans. Electron. Comput..

[2]  Naofumi Takagi,et al.  Design of high speed MOS multiplier and divider using redundant binary representation , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[3]  N. Takagi,et al.  A high-speed multiplier using a redundant binary adder tree , 1987 .

[4]  P. H. Ang,et al.  Generation of high speed CMOS multiplier-accumulators , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[5]  H. Edamatsu,et al.  A 33 Mflops Floating Point Processor Using Redundant Binary Representation , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[6]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[7]  Hiroto Yasuura,et al.  High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.

[8]  N. Bedard,et al.  Design of a high-speed arithmetic datapath , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[9]  A. Avizeinis,et al.  Signed Digit Number Representations for Fast Parallel Arithmetic , 1961 .

[10]  James E. Robertson,et al.  Logical design of a redundant binary adder , 1978, 1978 IEEE 4th Symposium onomputer Arithmetic (ARITH).

[11]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..