MUX Based Flash ADC for Reduction in Number of Comparators

A conventional N-bit flash analog to digital converter has been required the 2N number of resistors and 2N-1 number of preamplifiers as well as comparators. In this proposed work, a number of comparators could be reduced by introducing the multiplexer (MUX). This proposed work has only required the (2^(N-2) + 1) number of comparators. For 6-bit resolution, MUX based flash ADC requires a reduced number of comparators by 73%, respectively, compared with the traditional flash ADC. This proposed 6-bit ADC consists of a reference ladder circuit, a (2x1) multiplexer, 8 (4x1) multiplexer, 17 comparators and thermometer to binary encoder. The proposed 6-bit 200 MSPS ADC is designed and simulated in cadence tools with 1 V supply voltage using 90nm CMOS technology. The proposed work results into effective number of bits (ENOB) of 5.69 bit and figure of merit (FOM) of 0.019 pJ/conversion-step for 200 MS/s.

[1]  Yuh-Shyan Hwang,et al.  A New Low Power Flash ADC Using Multiple-Selection Method , 2007, 2007 IEEE Conference on Electron Devices and Solid-State Circuits.

[2]  Jong-In Song,et al.  Flash ADC architecture using multiplexers to reduce a preamplifier and comparator count , 2013, 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013).

[3]  E. Sail,et al.  A multiplexer based decoder for flash analog-to-digital converters , 2004, 2004 IEEE Region 10 Conference TENCON 2004..

[4]  Behzad Razavi,et al.  Design techniques for high-speed, high-resolution comparators , 1992 .

[5]  Kyusun Choi,et al.  A 1-GSPS CMOS flash A/D converter for system-on-chip applications , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

[6]  Reza Lotfi,et al.  Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  P.J. Hurst,et al.  A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[8]  A. Aditya,et al.  Implementation of low power Successive Approximation ADC for MAV's , 2013, 2013 International Conference on Signal Processing , Image Processing & Pattern Recognition.

[9]  Jong-In Kim,et al.  A time-domain latch interpolation technique for low power flash ADCs , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[10]  Denis C. Daly,et al.  A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy , 2009, IEEE Journal of Solid-State Circuits.

[11]  Mark Vesterbacka,et al.  Thermometer-to-binary decoders for flash analog-to-digital converters , 2007, 2007 18th European Conference on Circuit Theory and Design.

[12]  Jaewook Kim,et al.  Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  J. Jacob Wikner,et al.  CMOS Data Converters for Communications , 2000 .