VLSI prototyping of low-complexity wavelet transform on FPGA

In this paper, a low-complexity architecture using lifting step is proposed. The architecture makes use of existing lifting scheme and strategically schedules the MAC (multiplier adder cell) for its optimum use. It has been shown that the number of multiplier and adder are reduced to one half for implementing a lifting step. The proposed approach can be extended to other wavelet transforms implemented via lifting and it can be shown that better results are achieved.