On hardware implementation of fuzzy processing

Digital architecture of fuzzy processor is proposed. All blocks - fuzzy sets (triangular), rule strength calculation (minimum) and defuzzyfication (weighted sum) were implemented in VHDL, verified and synthesized for FPGA. Implementation of floating point division block appeared to be the most difficult part of the design. Partially concurrent and pipelined data flow provides competitive performance, with relatively little dependence on particular algorithm complexity.

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