A general-purpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all

A general-purpose vector-quantization (VQ) processor featuring high-speed and versatile winner search functions is presented. A new two-dimensionally bit-propagating scheme has been employed in the winner-take-all (WTA) circuit. As a result, the maximum/minimum value identification for 6 b 128 inputs in a single clock cycle has been accomplished, which is five times faster than the conventional approach (18 b comparison is carried out in three clock cycles). In addition, the new block addressing scheme developed in the present work enables various options in WTA operations. The chip was fabricated in a standard CMOS process and the operation was demonstrated by application to handwritten character recognition as an example.

[1]  K. Kotani,et al.  A parallel vector-quantization processor eliminating redundant calculations for real-time motion picture compression , 2000, IEEE Journal of Solid-State Circuits.

[2]  H. Onodera,et al.  A Memory-based Parallel Processor for Vector Quantization , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[3]  Tadashi Shibata,et al.  Intelligent Internet search applications based on VLSI associative processors , 2002, Proceedings 2002 Symposium on Applications and the Internet (SAINT 2002).

[4]  R. Canegallo,et al.  55GCPS CAM using 5b analog flash , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[5]  T. Morimoto,et al.  A fully-parallel vector quantization processor for real-time motion picture compression , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[6]  T. Ohmi,et al.  A parallel vector quantization processor eliminating redundant calculations for real-time motion picture compression , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).