Thermal modeling of self-heating in strained-silicon MOSFETs

Self-heating is a pressing issue for both the silicon-on-insulator (SOI) and Strained-Si technologies, where the devices are separated from the silicon substrate by poor thermal conducting layers. Although seemingly counterintuitive, the level of self-heating in a strained-Si transistor could be comparable with that of the SOI device due to the poor thermal conductivity of the thick Si/sub 0.8/Ge/sub 0.2/ underlayer (/spl sim/5 W/m-K). The lateral thermal conduction in strained-Si layer of thickness near 10-20 nm would somewhat reduce the maximum temperature rise in the device but is significantly reduced due to the phonon-boundary scattering. In the absence of effective tools for sub-continuum heat transfer modeling, reduced thermal conductivity values for thin silicon and Si/Si/sub 0.8/Ge/sub 0.2/ are used in a one-dimensional multi-fin model that accounts for the lateral conduction in the channel, source and drain as well as heat loss to the Si/sub 0.8/Ge/sub 0.2/ underlayer. This provides a simple yet effective tool for thermal simulations of the strained-Si transistors, which can also be extended to the SiGe-on-insulator (SGOI) technology.