Computing cache vulnerability to transient errors and its implication
暂无分享,去创建一个
[1] Dhiraj K. Pradhan,et al. Fault-tolerant computer system design , 1996 .
[2] G. Tyson,et al. Eager writeback-a technique for improving bandwidth utilization , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.
[3] Margaret Martonosi,et al. Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.
[4] R. Baumann. The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction , 2002, Digest. International Electron Devices Meeting,.
[5] Arun K. Somani,et al. Soft error sensitivity characterization for microprocessor dependability enhancement strategy , 2002, Proceedings International Conference on Dependable Systems and Networks.
[6] Joel Emer,et al. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[7] Narayanan Vijaykrishnan,et al. Analyzing soft errors in leakage optimized SRAM design , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..
[8] Sanjay J. Patel,et al. Characterizing the effects of transient faults on a high-performance processor pipeline , 2004, International Conference on Dependable Systems and Networks, 2004.