Hardware implementation of Boolean neural networks

Describes an approach for implementing Boolean Neural Networks on silicon. The hardware is based on a custom designed Field Programmable Logic Device (FPLD) which integrates 'synapses' and 'neurons' and allows random access to the weights during training. Networks are realised from arrays of the neural chip which are assembled on ceramic as Multi-Chip Modules (MCM) to provide expandability and flexibility. The hardware provides parallel computation of the 'neuron' outputs and promises significantly improved performance compared to purely software approaches.< >