An efficient probability framework for error propagation and correlation estimation

Soft error is becoming one of the major reliability concerns with continuously shrinking transistor size. Low level transient events may result in multiple correlated bit flips at high level. Considering this correlation effect is essential for accurate error rate estimation and efficient error mitigation. This paper proposes a novel framework to address this correlation issue at logic level. Based on the concept of error propagation function, graph transformation techniques are utilized to convert the error probability and correlation problem into the computation of signal probability and correlation. The experimental results show that compared with Monte-Carlo simulation, our approach is 72× faster, while the average inaccuracy of error probability estimation is below 0.006.

[1]  Kia Bazargan,et al.  Estimation and optimization of reliability of noisy digital circuits , 2009, 2009 10th International Symposium on Quality Electronic Design.

[2]  Joel S. Emer,et al.  The soft error problem: an architectural perspective , 2005, 11th International Symposium on High-Performance Computer Architecture.

[3]  B. Ricco,et al.  Estimate of signal probability in combinational logic networks , 1989, [1989] Proceedings of the 1st European Test Conference.

[4]  Sanjay J. Patel,et al.  Characterizing the effects of transient faults on a high-performance processor pipeline , 2004, International Conference on Dependable Systems and Networks, 2004.

[5]  John P. Hayes,et al.  Trigonometric method to handle realistic error probabilities in logic circuits , 2011, 2011 Design, Automation & Test in Europe.

[6]  Narayanan Vijaykrishnan,et al.  SEAT-LA: a soft error analysis tool for combinational logic , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[7]  Sanjukta Bhanja,et al.  Cascaded Bayesian inferencing for switching activity estimation with correlated inputs , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Radu Marculescu,et al.  Probabilistic modeling of dependencies during switching activity analysis , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  J. Hammersley SIMULATION AND THE MONTE CARLO METHOD , 1982 .

[10]  Massoud Pedram,et al.  Probabilistic error propagation in logic circuits using the Boolean difference calculus , 2008, 2008 IEEE International Conference on Computer Design.

[11]  Gábor Csárdi,et al.  The igraph software package for complex network research , 2006 .

[12]  Diana Marculescu,et al.  Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.

[14]  David Blaauw,et al.  An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[15]  Seyed Ghassem Miremadi,et al.  SCFIT: A FPGA-based fault injection technique for SEU fault model , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[16]  Sara Blanc,et al.  Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Kartik Mohanram,et al.  Reliability Analysis of Logic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[19]  Sanjukta Bhanja,et al.  Probabilistic Error Modeling for Nano-Domain Logic Circuits , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[20]  Xiaodong Li,et al.  SoftArch: an architecture-level tool for modeling and analyzing soft errors , 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

[21]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[22]  H. Asadi,et al.  Soft Error Derating Computation in Sequential Circuits , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[23]  Cecilia Metra,et al.  Multiple transient faults in logic: an issue for next generation ICs? , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).