High-throughput and hardware-efficient architecture of MQ arithmetic coder

Because of the feedback loops caused by iterative operations, MQ arithmetic coder usually acts as the performance bottleneck of the hardware architecture for JPEG2000 algorithm. According to the different features of the loops, this paper adopts different optimizing methods rather than general concurrent techniques to improve the hardware efficiency as well as throughput. Based on careful analysis of data dependency, circuit-level optimizations such as assistant loops, inverse multi branches selection (IMBS) are used to improve clock frequency. For the low hardware utilization caused by variable features of inside dataflow, reorganization of dataflow is performed and both the hardware-efficiency and the throughput are improved. The implementation result shows that the throughput of our design can exceed those based on traditional concurrent techniques. Moreover, the hardware utilization is much higher than exiting architectures.