Enhancing online error detection through area-efficient multi-site implications

We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.

[1]  Irith Pomeranz,et al.  On finding functionally identical and functionally opposite lines in combinational logic circuits , 1996, Proceedings of 9th International Conference on VLSI Design.

[2]  Giovanni Squillero,et al.  RT-Level ITC'99 Benchmarks and First ATPG Results , 2000, IEEE Des. Test Comput..

[3]  Nur A. Touba,et al.  Cost-effective approach for reducing soft error failure rate in logic circuits , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[4]  Yiorgos Makris,et al.  Concurrent fault detection in random combinational logic , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[5]  Jacob A. Abraham,et al.  A low-cost concurrent error detection technique for processor control logic , 2008, 2008 Design, Automation and Test in Europe.

[6]  Babak Falsafi,et al.  Dual use of superscalar datapath for transient-fault detection and recovery , 2001, MICRO.

[7]  Peter Rodgers,et al.  Constructing Area-Proportional Venn and Euler Diagrams with Three Circles , 2005 .

[8]  Irith Pomeranz,et al.  Reducing fault latency in concurrent on-line testing by using checking functions over internal lines , 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

[9]  Ilan Beer,et al.  FoCs: Automatic Generation of Simulation Checkers from Formal Specifications , 2000, CAV.

[10]  Kewal K. Saluja,et al.  An implementation and analysis of a concurrent built-in self-test technique , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[11]  T. N. Vijaykumar,et al.  Opportunistic transient-fault detection , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[12]  S. Katkoori,et al.  Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs , 2004, IEEE Transactions on Nuclear Science.

[13]  R. Iris Bahar,et al.  A Cost Effective Approach for Online Error Detection Using Invariant Relationships , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  John S. Liptay,et al.  A high-frequency custom CMOS S/390 microprocessor , 1997, IBM J. Res. Dev..

[15]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[16]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[17]  Edward J. McCluskey,et al.  Which concurrent error detection scheme to choose ? , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).