From Synchronous Specifications to Statically Scheduled Hard Real-Time Implementations

Hard real-time embedded systems are often designed as automatic control systems that can include both continuous and discrete parts. The functional specification of such systems is usually done in a conditioned data-flow formalism such as Simulink or Scade. These formalisms are either quasi-synchronous or synchronous, and they go beyond the classical data-flow model by introducing a form of conditional execution allowing the description of hierarchical execution modes. Specific real-time implementation approaches have been proposed for such formalisms, which exploit the hierarchical conditions to improve the generated code. We present one such approach which takes as input data-flow synchronous specifications and uses static scheduling heuristics to automatically produce efficient distributed real-time implementations. We explain how improving the analysis of the hierarchical conditions results in better implementations.

[1]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[2]  Joseph Y.-T. Leung,et al.  On the complexity of fixed-priority scheduling of periodic, real-time tasks , 1982, Perform. Evaluation.

[3]  Chung Laung Liu,et al.  Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment , 1989, JACM.

[4]  Albert Benveniste,et al.  Concurrency in Synchronous Systems , 2006, Formal Methods Syst. Des..

[5]  Marco Platzner,et al.  An EDF schedulability test for periodic tasks on reconfigurable hardware devices , 2006 .

[6]  Albert Benveniste,et al.  The synchronous approach to reactive and real-time systems , 1991 .

[7]  Yves Sorel,et al.  Load Balancing and Efficient Memory Usage for Homogeneous Distributed Real-Time Embedded Systems , 2008, 2008 International Conference on Parallel Processing - Workshops.

[8]  Laurent Arditi,et al.  Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System , 2001, FME.

[9]  Yves Sorel,et al.  Schedulability Analysis for Non-Preemptive Tasks under Strict Periodicity Constraints , 2008, 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications.

[10]  Robert de Simone,et al.  Clock-driven distributed real-time implementation of endochronous synchronous programs , 2009, EMSOFT '09.

[11]  Frédéric Boussinot,et al.  Distributed reactive machines , 1998, Proceedings Fifth International Conference on Real-Time Computing Systems and Applications (Cat. No.98EX236).

[12]  Daniel F. García,et al.  Worst-case utilization bound for EDF scheduling on real-time multiprocessor systems , 2000, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000.

[13]  Klaus Schneider,et al.  Proving the Equivalence of Microstep and Macrostep Semantics , 2002, TPHOLs.

[14]  Liliana Cucu-Grosjean,et al.  Periodic real-time scheduling: from deadline-based model to latency-based model , 2008, Ann. Oper. Res..

[15]  Petru Eles,et al.  Scheduling of conditional process graphs for the synthesis of embedded systems , 1998, DATE.

[16]  Stavros Tripakis,et al.  From simulink to SCADE/lustre to TTA: a layered approach for distributed embedded applications , 2003 .

[17]  José Nuno Oliveira,et al.  FME 2001: Formal Methods for Increasing Software Productivity , 2001, Lecture Notes in Computer Science.

[18]  Stephen A. Edwards,et al.  The synchronous languages 12 years later , 2003, Proc. IEEE.

[19]  Nicolas Halbwachs,et al.  Synchronous Programming of Reactive Systems , 1992, CAV.

[20]  Gérard Berry,et al.  The Esterel Synchronous Programming Language: Design, Semantics, Implementation , 1992, Sci. Comput. Program..

[21]  Yves Sorel,et al.  From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations , 2003, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings..

[22]  Jean-Christophe Le Lann,et al.  POLYCHRONY for System Design , 2003, J. Circuits Syst. Comput..

[23]  Apostolos A. Kountouris,et al.  Efficient scheduling of conditional behaviors for high-level synthesis , 2002, TODE.

[24]  Montek Singh,et al.  Generalized latency-insensitive systems for single-clock and multi-clock architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[25]  Zonghua Gu,et al.  Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[26]  Pascal Raymond,et al.  The synchronous data flow programming language LUSTRE , 1991, Proc. IEEE.

[27]  Roman Obermaisser,et al.  Event-Triggered and Time-Triggered Control Paradigms , 2004, Real-Time Systems Series.

[28]  Robert de Simone,et al.  Compositional Semantics of ESTEREL and Verification by Compositional Reductions , 1994, CAV.

[29]  Marc Pouzet,et al.  N-synchronous Kahn networks: a relaxed model of synchrony for real-time systems , 2006, POPL '06.

[30]  Thomas R. Shiple,et al.  Constructive analysis of cyclic circuits , 1996, Proceedings ED&TC European Design and Test Conference.

[31]  Alan Burns,et al.  Effective Analysis for Engineering Real-Time Fixed Priority Schedulers , 1995, IEEE Trans. Software Eng..

[32]  Amar Bouali,et al.  XEVE, an ESTEREL Verification Environment , 1998, CAV.

[33]  P. H. Lindsay Human Information Processing , 1977 .

[34]  Jim Grundy,et al.  Proceedings of the 9th International Conference on Theorem Proving in Higher Order Logics , 1996 .

[35]  Alberto L. Sangiovanni-Vincentelli,et al.  Extensible and scalable time triggered scheduling , 2005, Fifth International Conference on Application of Concurrency to System Design (ACSD'05).

[36]  Ellen M. Sentovich,et al.  Latch optimization in circuits generated from high-level descriptions , 1996, ICCAD 1996.