Tracking Uncertainty with Probabilistic Logic Circuit Testing

The diverse nature of the faults and defects that may occur at nanoscale ranges necessitates new techniques for ATPG. This article proposes an efficient technique that relies on a probabilistic approach to detect and diagnose nontraditional faults and defects.

[1]  Naresh R. Shanbhag,et al.  Soft-Error-Rate-Analysis (SERA) Methodology , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[3]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[4]  John P. Hayes,et al.  Transient fault characterization in dynamic noisy environments , 2005, IEEE International Conference on Test, 2005..

[5]  Bin Zhang,et al.  FASER: fast analysis of soft error susceptibility for cell-based designs , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[6]  C. Metra,et al.  A model for transient fault propagation in combinatorial logic , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[7]  Vijay V. Vazirani,et al.  Approximation Algorithms , 2001, Springer Berlin Heidelberg.

[8]  Sarita Thakar,et al.  On the generation of test patterns for combinational circuits , 1993 .

[9]  M. Degroot.  Optimal Statistical Decisions , 1970 .

[10]  Éva Tardos,et al.  Algorithm design , 2005 .