VHDL for Simulation, Synthesis, and Formal Proofs of Hardware

Preface. Introduction. Evolutionary Processes in Language, Software, and System Design F.E. Marschner. Part I: Simulation. Timing Constraint Checks in VHDL -- a Comparative Study F. Liu, A. Pawlak. Using Formalized Timing Diagrams in VHDL Simulation M. Dufresne, K. Khordoc, E. Cerny. Switch-Level Models in Multi-Level VHDL Simulations K. Khordoc, M. Biotteau, E. Cerny. Bi-Directional Switches in VHDL Using the 46 Value System A. Stanculescu. Systems Real Time Analysis with VHDL Generated from Graphical SA-VHDL M. Sipola, J.-P. Soininen, J. Kivela. Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design P. Connors, S. Nayak, J. Kraley, V. Berman. Part II: Synthesis. A VHDL-Driven Synthesis Environment H. Konuk, F.E. Marschner. VHDL Specific Issues in High Level Synthesis A. Postula. ASIC Design Using Silicon 1076 R.A. Cottrell. Generating VHDL for Simulation and Synthesis from a High-Level DSP Design Tool L. Lundberg. Aspects of Optimization and Accuracy for VHDL Synthesis J. Eliott, P. Harper. Part III: Formal Verifications and Semantics. Symbolic Computation of Hierarchical and Interconnected FSMS A. Debreil, C. Berthet, A. Jerraya. Formal Semantics of VHDL Timing Constructs A. Salem, D. Borrione. A Structural Information Model of VHDL R.A.J. Marshall, H.J. Kahn. Formal Verification of VHDL Descriptions in Boyer-Moore: First Results D. Borrione, L. Pierre, A. Salem. Developing a Formal Semantic Definition of VHDL P.A. Wilsey. Part IV: Systems Level Design and Modelling. Approaching System Level Design F.J. Rammig. Incremental Design -- Application of a Software-Based Method for High-LevelHardware Design with VHDL A. Hohl. Introducing CASCADE Control Graph in VHDL C. Le Faou, J. Mermet.