A high-speed IDDQ sensor implementation

This paper presents an effective IDDQ sensor design implemented using a 0.35 /spl mu/m process. A straightforward feedback scheme minimizes the effect of process variations. Independent structures permit one to monitor the basic characteristics of the IDDQ sensor, i.e., resolution and speed, and to carry out a 20k-gate floppy-disk controller IDDQ test separately. Simulation and test results show accuracy better than /spl plusmn/10 /spl mu/A at 50 MHz in a 1 mA IDDQ measurement range.

[1]  K. Kinoshita,et al.  100 MHz IDDQ sensor design with 1 /spl mu/A resolution for BIST applications , 1998, Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232).

[2]  Y. Deval,et al.  Off chip monitors and built in current sensors for analogue and mixed signal testing , 1998, Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232).

[3]  Robert C. Aitken,et al.  IDDQ and AC scan: the war against unmodelled defects , 1996, Proceedings International Test Conference 1996. Test and Design Validity.