Circuit design of routing switches

This paper examines circuit design of buffered routing switches in symmetrical, island-style FPGAs. The effects of switch size, tile length, level-restoring, and slow input slew rates are examined. Two new fanin-based switch designs are used to eliminate nearly all of the increase in delay that arises from fanout with a previous switch design. Alternating between buffers and pass transistors is shown to improve connection delay without fanout by 25%. To take advantage of this, we propose schemes to replace some buffers with pass transistors to simultaneously reduce area and delay. Routing a suite of MCNC benchmark circuits shows that 14% in area-delay, or 7% in delay can be saved using the new switch schemes. Alternatively, approximately 13% in area can be saved with no degradation to delay.

[1]  Guy Lemieux,et al.  Using sparse crossbars within LUT , 2001, FPGA '01.

[2]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[3]  Richard C. Li,et al.  A novel predictable segmented FPGA routing architecture , 1998, FPGA '98.

[4]  Zvonko G. Vranesic,et al.  Modelling Routing Delays in SRAM-based FPGAs , 1993 .

[5]  Jonathan Rose,et al.  Mixing buffers and pass transistors in FPGA routing architectures , 2001, FPGA '01.

[6]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[7]  Vaughn Betz,et al.  Circuit design, transistor sizing and wire layout of FPGA interconnect , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[8]  David Lewis,et al.  Using Sparse Crossbars within LUT Clusters , 2001 .

[9]  Vaughn Betz,et al.  Speed and area tradeoffs in cluster-based FPGA architectures , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Steven Trimberger,et al.  Architecture issues and solutions for a high-capacity FPGA , 1997, FPGA '97.

[11]  Kenneth W. Martin,et al.  Digital Integrated Circuit Design , 1999 .

[12]  J. Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2000, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[14]  P. Chow,et al.  The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[15]  A. El Gamal,et al.  Regenerative feedback repeaters for programmable interconnections , 1995 .