Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects

For future miniaturization of electronic systems using 3D chip stacking, new fine-pitch materials for through-silicon-via (TSV) applications are likely required. In this paper, we propose a novel carbon nanotube (CNT)/copper nanocomposite material consisting of high aspect ratio, vertically aligned CNT bundles coated with copper. These bundles, consisting of hundreds of tiny CNTs, were uniformly coated by copper through electroplating, and aspect ratios as high as 300:1 were obtained. The resistivity of this nanomaterial was found to be as low as ∼10(-8) Ω m, which is of the same order of magnitude as the resistivity of copper, and its temperature coefficient was found to be only half of that of pure copper. The main advantage of the composite TSV nanomaterial is that its coefficient of thermal expansion (CTE) is similar to that of silicon, a key reliability factor. A finite element model was set up to demonstrate the reliability of this composite material and thermal cycle simulations predicted very promising results. In conclusion, this composite nanomaterial appears to be a very promising material for future 3D TSV applications offering both a low resistivity and a low CTE similar to that of silicon.

[1]  Jin Kawakita,et al.  Through silicon via filling methods with metal/polymer composite for three-dimensional LSI , 2014 .

[2]  P. Avouris,et al.  Carbon-based electronics. , 2007, Nature nanotechnology.

[3]  Jia Wei,et al.  3D system-in-package design using stacked silicon submount technology , 2015 .

[4]  Chang-Woo Lee,et al.  High-speed TSV filling with molten solder , 2012 .

[5]  Nobuaki Takahashi,et al.  Low-cost TSV process using electroless Ni plating for 3D stacked DRAM , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[6]  C. Selvanayagam,et al.  Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps , 2009, IEEE Transactions on Advanced Packaging.

[7]  H. Kawarada,et al.  Low temperature grown carbon nanotube interconnects using inner shells by chemical mechanical polishing , 2007 .

[8]  K. Jeppson,et al.  Tape-Assisted Transfer of Carbon Nanotube Bundles for Through-Silicon-Via Applications , 2015, Journal of Electronic Materials.

[9]  Eby G. Friedman,et al.  Three-dimensional Integrated Circuit Design , 2008 .

[10]  Bin Liu,et al.  Thermal Expansion of Single Wall Carbon Nanotubes , 2004 .

[11]  Flynn P. Carson,et al.  3-D Stacked Package Technology and Trends , 2009, Proceedings of the IEEE.

[12]  Lingling Sun,et al.  Electrothermal modelling and characterisation of submicron through-silicon carbon nanotube bundle vias for three-dimensional ICs , 2014 .

[13]  R. Noble,et al.  Progress and challenges of tungsten-filled through-silicon via , 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

[14]  Ronald J. Gutmann,et al.  Rensselaer 3D Integration Processes , 2008 .

[15]  Li Li,et al.  Modeling and characterization of CNT-based TSV for high frequency applications , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[16]  Sang-Bock Cho,et al.  Development of hybrid electrical model for CNT based Through Silicon Vias , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

[17]  Teng Wang,et al.  Through silicon vias filled with planarized carbon nanotube bundles , 2009, Nanotechnology.

[18]  K. Koziol,et al.  A computational study of the quantum transport properties of a Cu–CNT composite† †Electronic supplementary information (ESI) available. See DOI: 10.1039/c5cp01470k Click here for additional data file. , 2015, Physical chemistry chemical physics : PCCP.

[19]  Chun-Li Liu Screening beneficial dopants to Cu interconnects by modeling , 2002 .

[20]  C. Basaran,et al.  Joule heating in single-walled carbon nanotubes , 2009 .

[21]  L. Ladani,et al.  Cohesive Zone Model for the Interface of Multiwalled Carbon Nanotubes and Copper: Molecular Dynamics Simulation , 2014 .

[22]  D. Henry,et al.  Polymer filling of medium density through silicon via for 3D-packaging , 2009, 2009 11th Electronics Packaging Technology Conference.

[23]  Tong-Yi Zhang,et al.  Fabrication of high aspect ratio through-wafer copper interconnects by reverse pulse electroplating , 2009 .

[24]  J. Robertson,et al.  Carbon nanotube growth for through silicon via application , 2013, Nanotechnology.

[25]  Mitsumasa Koyanagi,et al.  Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs , 2008 .

[26]  P. Avouris,et al.  Current saturation and electrical breakdown in multiwalled carbon nanotubes. , 2001, Physical review letters.

[27]  J. Miao,et al.  Aligned carbon nanotubes for through-wafer interconnects , 2007 .

[28]  Teng Wang,et al.  Paper-mediated controlled densification and low temperature transfer of carbon nanotube forests for electronic interconnect application , 2013 .

[29]  Takeo Yamada,et al.  One hundred fold increase in current carrying capacity in a carbon nanotube–copper composite , 2013, Nature Communications.

[30]  Y. Feng,et al.  Fabrication and electrical performance of through silicon via interconnects filled with a copper/carbon nanotube composite , 2015 .

[31]  Makoto Motoyoshi,et al.  Through-Silicon Via (TSV) , 2009, Proceedings of the IEEE.

[32]  Teng Wang,et al.  Carbon nanotubes for electronics manufacturing and packaging: from growth to integration , 2013 .

[33]  H. Reichl,et al.  High aspect ratio TSV copper filling with different seed layers , 2008, 2008 58th Electronic Components and Technology Conference.

[34]  Kwang-Ho Kwon,et al.  Dual etch processes of via and metal paste filling for through silicon via process , 2011 .

[35]  Changhong Liu,et al.  Highly oriented carbon nanotube papers made of aligned carbon nanotubes , 2008, Nanotechnology.

[36]  K. Jeppson,et al.  Through-Silicon Vias Filled With Densified and Transferred Carbon Nanotube Forests , 2012, IEEE Electron Device Letters.

[37]  Fully back-end TSV process by Cu electro-less plating for 3D smart sensor systems , 2013 .

[38]  Di Jiang,et al.  Vertically Stacked Carbon Nanotube-Based Interconnects for Through Silicon Via Application , 2015, IEEE Electron Device Letters.

[39]  F. Banhart Interactions between metals and carbon nanotubes: at the interface between old and new materials. , 2009, Nanoscale.

[40]  Baowen Li,et al.  Thermal expansion in single-walled carbon nanotubes and graphene: Nonequilibrium Green's function approach , 2009, 0909.1917.

[41]  L. Ladani,et al.  Interfacial Strength Between Single Wall Carbon Nanotubes and Copper Material: Molecular Dynamics Simulation , 2013 .