A robust and low power 7T SRAM cell design

In this paper, we propose a new seven transistors (7T) static random access memory (SRAM) cell that improves read stability and write ability of the conventional 6T SRAM cell. Separating read and write access transistors in this cell solves the conflict of access transistor sizing. Therefore, large write and small read access transistors are chosen leading to read stability and write ability enhancement. Moreover, by isolating the storage node from the read path, more improvement in the read stability is achieved. Single ended write operation in this cell leads to reduction in the number of write drivers. In order to further improve the write ability, a virtual ground for one of the inverters is used. This strategy weakens the positive feedback and enhances the write ability of the cell. HSPICE Simulations in 90 nm CMOS technology show 80% and 54.9% improvement for the proposed structure with respect to the conventional 6T cell in the read stability and write ability, respectively, at the supply voltage of 500 mV. Using the virtual ground in this design causes leakage power reduction for each cell by stacking effect. The virtual ground is shared among all the cells in a row in order to lower the SRAM block power and relax the area and power overhead of extra transistor that used. The HSPICE simulation results also show 12.35% improvement in the static power at the 500 mV supply voltage.