Annealing-based heuristics and genetic algorithms for circuit partitioning in parallel test generation

Abstract In this paper simulated annealing and genetic algorithms are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biology, respectively, and are the most popular meta-heuristics or general-purpose optimization strategies. A hybrid algorithm for circuit partitioning, which uses tabu search to improve the simulated annealing meta-heuristics, is also proposed and compared with pure tabu search and simulated annealing algorithms, and also with a genetic algorithm. The solutions obtained are compared and evaluated by including the hybrid partitioning algorithm in a parallel test generator which is used to determine the test patterns for the circuits of the frequently used ISCAS benchmark set.

[1]  Charles M. Fiduccia,et al.  A linear-time heuristic for improving network partitions , 1988, 25 years of DAC.

[2]  Hyunchul Shin,et al.  A simple yet effective technique for partitioning , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[3]  John H. Holland,et al.  Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence , 1992 .

[4]  R. Sarnath,et al.  Proceedings of the International Conference on Parallel Processing , 1992 .

[5]  Dan Boneh,et al.  On genetic algorithms , 1995, COLT '95.

[6]  R. M. Mattheyses,et al.  A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.

[7]  Kathryn A. Dowsland.  Modem heuristic techniques for combinatorial problems , 1993 .

[8]  George Karypis,et al.  Introduction to Parallel Computing , 1994 .

[9]  Celso C. Ribeiro,et al.  A graph partitioning heuristic for the parallel pseudo-exhaustive logical test of VLSI combinational circuits , 1994, Ann. Oper. Res..

[10]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[11]  James H. Aylor,et al.  Parallel-processing techniques for automatic test pattern generation , 1992, Computer.

[12]  C. Reeves.  Modern heuristic techniques for combinatorial problems , 1993 .

[13]  Julio Ortega,et al.  Parallel test generation using circuit partitioning and spectral techniques , 1998, Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 -.

[14]  Scott F. Midkiff,et al.  Processor and Link Assignment in Multicomputers Using Simulated Annealing , 1988, ICPP.

[15]  D. E. Goldberg,et al.  Genetic Algorithms in Search , 1989 .

[16]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[17]  Laura A. Sanchis,et al.  Multiple-Way Network Partitioning with Different Cost Functions , 1993, IEEE Trans. Computers.

[18]  Brian W. Kernighan,et al.  An efficient heuristic procedure for partitioning graphs , 1970, Bell Syst. Tech. J..

[19]  D. E. Goldberg,et al.  Optimization and Machine Learning , 2022 .

[20]  Vipin Kumar,et al.  Scalable Load Balancing Techniques for Parallel Computers , 1994, J. Parallel Distributed Comput..

[21]  Brian L. Mark,et al.  An efficient eigenvector approach for finding netlist partitions , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Emile H. L. Aarts,et al.  Simulated annealing and Boltzmann machines - a stochastic approach to combinatorial optimization and neural computing , 1990, Wiley-Interscience series in discrete mathematics and optimization.

[23]  Constantine D. Polychronopoulos,et al.  Efficient circuit partitioning algorithms for parallel logic simulation , 1989, Proceedings of the 1989 ACM/IEEE Conference on Supercomputing (Supercomputing '89).

[24]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning: a survey , 1995, Integr..

[25]  Cecilia R. Aragon,et al.  Optimization by Simulated Annealing: An Experimental Evaluation; Part I, Graph Partitioning , 1989, Oper. Res..

[26]  Laura A. Sanchis,et al.  Multiple-Way Network Partitioning , 1989, IEEE Trans. Computers.

[27]  C. Gil,et al.  Algebraic test-pattern generation based on the Reed-Muller spectrum , 1998 .

[28]  David S. Johnson,et al.  Computers and In stractability: A Guide to the Theory of NP-Completeness. W. H Freeman, San Fran , 1979 .

[29]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[30]  Andrew B. Kahng,et al.  Recent developments in netlist partitioning: a survey , 1995 .