A 200 Mb/s PRML read/write channel IC

The hard disk drive industry is looking at synchronous design techniques (PRML) with a view to increasing storage density. Currently the high performance commercial read/write channels use (0, 4/4) codes to achieve up to 120 Mb/s data transfer rates. This paper describes a fully integrated read/write channel IC that operates at over 200 Mb/s. The single-chip solution in 0.51 /spl mu/m BiCMOS, has 20 mm/sup 2/ die and uses 0.85 W at 200 Mb/s.

[1]  D. Browning,et al.  A 72 Mb/s PRML disk-drive channel chip with an analog sampled-data signal processor , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[2]  Jacques C. Rudell,et al.  A 50 MHz eight-tap adaptive equalizer for partial-response channels , 1995 .

[3]  Robert Andrew Kertis,et al.  A 16 MB/s PRML read/write data channel , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.