As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous size, and thus, to scale well. This paper presents an open-source framework zamiaCAD based on a scalable model that includes both, a comprehensive elaboration front-end for RTL design and design processing back-end flows. The persistence and scalability are guaranteed by a custom-designed and highly optimized object database. As an HDL-centric framework it follows the concept of non-intrusiveness. In this paper, we discuss in detail the concepts of design elaboration into the scalable design model and present an evaluation of the model for static analysis as one of the back-end applications. Experimental results on very large designs show that zamiaCAD compares favorable to other frameworks with respect to the scalability aspects.
[1]
R. Rudell,et al.
Multiple-Valued Logic Minimization for PLA Synthesis
,
1986
.
[2]
Daniel Brand,et al.
BooleDozer: Logic synthesis for ASICs
,
1996,
IBM J. Res. Dev..
[3]
Melvin A. Breuer,et al.
Digital system design automation : languages, simulation & data base
,
1975
.
[4]
Ronald Fagin,et al.
Extendible hashing—a fast access method for dynamic files
,
1979,
ACM Trans. Database Syst..
[5]
Giovanni Squillero,et al.
RT-Level ITC'99 Benchmarks and First ATPG Results
,
2000,
IEEE Des. Test Comput..