A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
暂无分享,去创建一个
[1] D.E. Atkins. Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods , 1970, IEEE Transactions on Computers.
[2] Tomás Lang,et al. Digit-recurrence dividers with reduced logical depth , 2005, IEEE Transactions on Computers.
[3] Tomás Lang,et al. Low-Power Divider , 1999, IEEE Trans. Computers.
[4] Michael J. Schulte,et al. High-speed multioperand decimal adders , 2005, IEEE Transactions on Computers.
[5] Eric M. Schwarz,et al. A decimal floating-point specification , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.
[6] Michael J. Schulte,et al. Decimal floating-point square root using Newton-Raphson iteration , 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).
[7] M. Ercegovac,et al. Division and Square Root: Digit-Recurrence Algorithms and Implementations , 1994 .
[8] N. Burgess,et al. Design issues in radix-4 SRT square root & divide unit , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).
[9] James Demmel,et al. IEEE Standard for Floating-Point Arithmetic , 2008 .
[10] F.Y. Busaba,et al. The IBM z900 decimal arithmetic unit , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).
[11] Michael J. Schulte,et al. Decimal floating-point division using Newton-Raphson iteration , 2004, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004..
[12] Michael F. Cowlishaw,et al. Decimal floating-point: algorism for computers , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.
[13] Michael J. Schulte,et al. Decimal multiplication with efficient partial product generation , 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).
[14] Neil Weste,et al. Principles of CMOS VLSI Design , 1985 .