A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture

In this work, we present a radix-10 division unit that is based on the digit-recurrence algorithm. The previous decimal division designs do not include recent developments in the theory and practice of this type of algorithm, which were developed for radix-2k dividers. In addition to the adaptation of these features, the radix-10 quotient digit is decomposed into a radix-2 digit and a radix-5 digit in such a way that only five and two times the divisor are required in the recurrence. Moreover, the most significant slice of the recurrence, which includes the selection function, is implemented in radix-2, avoiding the additional delay introduced by the radix-10 carry-save additions and allowing the balancing of the paths to reduce the cycle delay. The results of the implementation of the proposed radix-10 division unit show that its latency is close to that of radix-16 division units (comparable dynamic range of significant) and it has a shorter latency than a radix-10 unit based on the Newton-Raphson approximation

[1]  D.E. Atkins Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods , 1970, IEEE Transactions on Computers.

[2]  Tomás Lang,et al.  Digit-recurrence dividers with reduced logical depth , 2005, IEEE Transactions on Computers.

[3]  Tomás Lang,et al.  Low-Power Divider , 1999, IEEE Trans. Computers.

[4]  Michael J. Schulte,et al.  High-speed multioperand decimal adders , 2005, IEEE Transactions on Computers.

[5]  Eric M. Schwarz,et al.  A decimal floating-point specification , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[6]  Michael J. Schulte,et al.  Decimal floating-point square root using Newton-Raphson iteration , 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

[7]  M. Ercegovac,et al.  Division and Square Root: Digit-Recurrence Algorithms and Implementations , 1994 .

[8]  N. Burgess,et al.  Design issues in radix-4 SRT square root & divide unit , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[9]  James Demmel,et al.  IEEE Standard for Floating-Point Arithmetic , 2008 .

[10]  F.Y. Busaba,et al.  The IBM z900 decimal arithmetic unit , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

[11]  Michael J. Schulte,et al.  Decimal floating-point division using Newton-Raphson iteration , 2004, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004..

[12]  Michael F. Cowlishaw,et al.  Decimal floating-point: algorism for computers , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[13]  Michael J. Schulte,et al.  Decimal multiplication with efficient partial product generation , 2005, 17th IEEE Symposium on Computer Arithmetic (ARITH'05).

[14]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .