EDSU: Error detection and sampling unified flip-flop with ultra-low overhead
暂无分享,去创建一个
[1] David M. Bull,et al. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.
[2] Massimo Alioto,et al. Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] Sanjay Pant,et al. A self-tuning DVS processor using delay-error detection and correction , 2005, IEEE Journal of Solid-State Circuits.
[4] Dennis Sylvester,et al. Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails , 2014, IEEE Journal of Solid-State Circuits.
[5] Kwanyeob Chae,et al. A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[6] David Blaauw,et al. 8.8 iRazor: 3-transistor current-based error detection and correction in an ARM Cortex-R4 processor , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).
[7] Youhua Shi,et al. Timing monitoring paths selection for wide voltage IC , 2016, IEICE Electron. Express.
[8] Masanori Hashimoto,et al. PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices , 2013, IEICE Electron. Express.
[9] Mingoo Seok,et al. Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique , 2015, IEEE Journal of Solid-State Circuits.
[10] K.A. Bowman,et al. Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance , 2009, IEEE Journal of Solid-State Circuits.
[11] Soraya Ghiasi,et al. A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.