Impact of random telegraph noise on write stability in Silicon-on-Thin-BOX (SOTB) SRAM cells at low supply voltage in sub-0.4V regime
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Nobuyuki Sugii | Masaharu Kobayashi | Toshiro Hiramoto | Takuya Saraya | Shiro Kamohara | Hideki Makiyama | Yoshiki Yamamoto | Hidekazu Oda | Tomoko Mizutani | Hao Qiu | Tomohiro Yamashita | T. Saraya | T. Hiramoto | M. Kobayashi | H. Oda | Hao Qiu | T. Mizutani | Yoshiki Yamamoto | H. Makiyama | T. Yamashita | S. Kamohara | N. Sugii
[1] K. Takeuchi,et al. Direct Measurement of Correlation Between SRAM Noise Margin and Individual Cell Transistor Variability by Using Device Matrix Array , 2011, IEEE Transactions on Electron Devices.