A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement

Achieving high reliability across environmental variations and over aging in physical unclonable functions (PUFs) remains a challenge for PUF designers. The conventional method to improve PUF reliability is to use powerful error correction codes (ECC) to correct the errors in the raw response from the PUF core. Unfortunately, these ECC blocks generally have high VLSI overheads, which scale up quickly with the error correction capability. Alternately, researchers have proposed techniques to increase the reliability of the PUF core, and thus significantly reduce the required strength (and complexity) of the ECC. One method of increasing the reliability of the PUF core is to use normally detrimental IC aging effects to reinforce the desired (or "golden") response of the PUF by altering the PUF circuit characteristics permanently and hence making the PUF more reliable. In this work, we present a PUF response reinforcement technique based on hot carrier injection (HCI) which can reinforce the PUF golden response in short stress times (i.e., tens of seconds), without impacting the surrounding circuits, and that has high permanence (i.e., does not degrade significantly over aging). We present a self-contained HCI-reinforcement-enabled PUF circuit based on sense amplifiers (SA) which autonomously self-reinforces with minimal external intervention. We have fabricated a custom ASIC testchip in 65nm bulk CMOS with the proposed PUF design. Measured results show high reliability across environmental variations and accelerated aging, as well as good uniqueness and randomness. For example, 1600 SA elements, after being HCI stressed for 125s, show 100% reliability (zero errors) across ±20% voltage variations a temperature range of -20°C to 85°C.

[1]  Ahmad-Reza Sadeghi,et al.  Efficient Helper Data Key Extractor on FPGAs , 2008, CHES.

[2]  Ingrid Verbauwhede,et al.  Experimental evaluation of Physically Unclonable Functions in 65 nm CMOS , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

[3]  Srinivas Devadas,et al.  Secure and robust error correction for physical unclonable functions , 2010, IEEE Design & Test of Computers.

[4]  Leyla Nazhandali,et al.  Circuit-level techniques for reliable Physically Uncloneable Functions , 2009, 2009 IEEE International Workshop on Hardware-Oriented Security and Trust.

[5]  G. Edward Suh,et al.  Extracting secret keys from integrated circuits , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Ken Takeuchi,et al.  A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy , 2012, 2012 IEEE International Solid-State Circuits Conference.

[7]  G.-J. Schrijen,et al.  Physical Unclonable Functions and Public-Key Crypto for FPGA IP Protection , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[8]  Ingrid Verbauwhede,et al.  PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator , 2012, CHES.

[9]  Marcel J. M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[10]  Ken Mai,et al.  Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS , 2012, 2012 IEEE International Symposium on Hardware-Oriented Security and Trust.

[11]  Ken Mai,et al.  Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses , 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[12]  R. W. Keyes,et al.  Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics , 1975 .

[13]  M. Ieong,et al.  Modeling line edge roughness effects in sub 100 nanometer gate length devices , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).

[14]  M. Nelhiebel,et al.  Understanding temperature acceleration for NBTI , 2011, 2011 International Electron Devices Meeting.

[15]  Jorge Guajardo,et al.  FPGA Intrinsic PUFs and Their Use for IP Protection , 2007, CHES.

[16]  Sani R. Nassif,et al.  Characterizing Process Variation in Nanometer CMOS , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[17]  Srinivas Devadas,et al.  Silicon physical random functions , 2002, CCS '02.

[18]  Yevgeniy Dodis,et al.  Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Other Noisy Data , 2004, EUROCRYPT.

[19]  Marten van Dijk,et al.  A technique to build a secret key in integrated circuits for identification and authentication applications , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[20]  Yu Cao,et al.  Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.

[21]  Srinivas Devadas,et al.  Lightweight and Secure PUF Key Storage Using Limits of Machine Learning , 2011, CHES.

[22]  Daniel E. Holcomb,et al.  Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers , 2009, IEEE Transactions on Computers.

[23]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[24]  Suela Kodra.  Fuzzy extractors : How to generate strong keys from biometrics and other noisy data , 2015 .

[25]  Ken Mai,et al.  Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS , 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.