A scaled 0.6 /spl mu/m high speed PLD technology using single-poly EEPROM's

A 0.6 /spl mu/m CMOS single-polycide, double-metal, EEPROM technology for Programable Logic Device applications is described. A channel-stop implantation through an optimized LOCOS, and a compensated P-well profile at the N+/P junction, results in an aggressive 1.5 /spl mu/m field isolation pitch that satisfies the 12.5 V high-voltage requirement. The FN tunneling currents allow on-chip high-voltage generation from a single power supply for ISP applications. The EPM7032A and EPM7128E PLD products propagation delay time of 4.4 nsec and 6.8 nsec respectively, are the fastest reported at 32 and 128 macro-cell densities.