An efficient algorithm for custom instruction enumeration

In order to meet growing market demands in flexibility and performance, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instruction that can be implemented in special hardware unit is a vital component for improving performance in extensible processors. The key issue involved is to generate and select automatically custom instructions from high-level application code. In this paper, we propose a new efficient algorithm for automatic generation of all candidate instructions (or patterns). Our pattern generation algorithm identifies all feasible connected and disjoint patterns under different constraints. Compared to a previously proposed well-known algorithm, our algorithm solves the problem more efficiently by taking advantage of topological property of data flow graph (DFG) as well as overcoming the drawbacks of the previously proposed algorithm.

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