Demand code paging for NAND flash in MMU-less embedded systems
暂无分享,去创建一个
[1] Apala Guha,et al. Reducing Exit Stub Memory Consumption in Code Caches , 2007, HiPEAC.
[2] Jack W. Davidson,et al. Fragment cache management for dynamic binary translators in embedded systems with scratchpad , 2007, CASES '07.
[3] Chanik Park,et al. Cost-efficient memory architecture design of NAND flash memory embedded systems , 2003, Proceedings 21st International Conference on Computer Design.
[4] Mary Lou Soffa,et al. Retargetable and reconfigurable software dynamic translation , 2003, International Symposium on Code Generation and Optimization, 2003. CGO 2003..
[5] Kim M. Hazelwood,et al. A dynamic binary instrumentation engine for the ARM architecture , 2006, CASES '06.
[6] Chanik Park,et al. Energy-aware demand paging on NAND flash-based embedded storages , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[7] Bruce R. Childers,et al. Compact binaries with code compression in a software dynamic translator , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[8] Chanik Park,et al. A Re-configurable FTL (Flash Translation Layer) Architecture for NAND Flash based Applications , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).
[9] Sang Lyul Min,et al. Compiler-assisted demand paging for embedded systems with flash memory , 2004, EMSOFT '04.
[10] Sivan Toledo,et al. Characterizing the Performance of Flash Memory Storage Devices and Its Impact on Algorithm Design , 2008, WEA.
[11] Jack W. Davidson,et al. Reducing pressure in bounded DBT code caches , 2008, CASES '08.
[12] Ilhoon Shin,et al. SWL: a search-while-load demand paging scheme with NAND flash memory , 2007, LCTES '07.
[13] Naehyuck Chang,et al. Demand paging for OneNANDTM Flash eXecute-in-place , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[14] Anant Agarwal,et al. Software-based instruction caching for embedded processors , 2006, ASPLOS XII.
[15] Bruce R. Childers,et al. Heterogeneous code cache: Using scratchpad and main memory in dynamic binary translators , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[16] Apala Guha,et al. DBT path selection for holistic memory efficiency and performance , 2010, VEE '10.