A novel linearization technique for linear/pseudo-linear RF CMOS power amplifiers

A novel linearization technique for linear and pseudo-linear CMOS power amplifiers (PAs) is presented. The proposed technique uses the third-order harmonic of the PA output to generate a signal, which compensates the nonlinear component at the fundamental frequency of the PA output. The reconstructed signal is then subtracted from the output of the PA to cancel out its nonlinear component. A class-AB CMOS power amplifier, incorporating this technique, is designed and fabricated in a standard 0.18 /spl mu/m CMOS process. Experimental results of this class-AB PA at 900 MHz are presented. A two-tone test with frequency spacing of 1 MHz shows a 12-dB reduction of the IMD3 component.

[1]  Paul A. Goud,et al.  Power Amplifier Linearization using , 1993 .

[2]  Wing Shing Chan,et al.  New linearization method using interstage second harmonic enhancement , 1998 .

[3]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[4]  K.G. Voyce,et al.  Power amplifier linearization using IF feedback , 1989, IEEE MTT-S International Microwave Symposium Digest.

[5]  Tanaka,et al.  A Linearization Technique For CMOS RF Power Amplifiers , 1997, Symposium on VLSI Circuits.

[6]  Simsek Demir,et al.  A mathematical characterization and analysis of a feedforward circuit for CDMA applications , 2003 .

[7]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[8]  Fadhel M. Ghannouchi,et al.  Optimization of feedforward amplifier power efficiency on the basis of drive statistics , 2003 .

[9]  R.G. Meyer,et al.  Intermodulation distortion in current-commutating CMOS mixers , 2000, IEEE Journal of Solid-State Circuits.

[10]  Pietro Andreani,et al.  A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[11]  Lars Sundström,et al.  Design and implementation of a CMOS power feedback linearization IC for RF power amplifiers , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[12]  Antonio Valdovinos,et al.  Performance of a new digital baseband predistorter using calibration memory , 2001, IEEE Trans. Veh. Technol..

[13]  Tony S. H. Lee,et al.  The design of cmos radio-frequency integrated circuits"cambridge university press , 1998 .

[14]  Wu-Shiung Feng,et al.  A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).