A reconfigurable 10–12b 0.4–44MS/s pipelined ADC with 0.35–0.5pJ/step in 1.2V 90nm digital CMOS

This pipelined ADC is reconfigurable over sampling frequencies of 0.4–44 MS/s and resolutions of 10–12 bits, thus targeting multi-standard wireless terminals. Fabricated in 1.2-V 90-nm digital CMOS, it achieves a competitive FOM of 0.35–0.5 pJ/conversion step over its wide reconfigurability space. For power scalability, the ADC bandwidth and resolution are reconfigured using current-scaling and stage-bypass methods, respectively. The following techniques are also introduced to achieve this low-power performance for the ADC over its wide reconfigurability space, and to enable its implementation in low-voltage nanometer CMOS: 1) pseudo-cascode compensation for the low-power design of low-voltage current-scalable opamps; 2) design of switched-capacitor dynamic comparators with low input loading; 3) low-power digital background gain calibration to enable designing the ADC using low-gain/low-power opamps.