A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency

A bipolar LSI chip which achieves 2.5 times the normal clock frequency by means of wave pipelining without the use of additional storage elements is described. In wave pipelining, multiple coherent waves of data are placed between storage elements by clocking the circuit faster than the propagation delay of the combinational logic. If all the propagation paths from the combinational circuit inputs to outputs have approximately the same delay, each wave propagates uniformly to the outputs without interfering with adjacent waves. The wave pipelining concept has been tested using a demonstration chip. Compared to an implementation using ordinary pipelining, a wave-pipelined circuit reduces the latency, area, and clock distribution required by pipeline registers or latches. >