An interval-based diagnosis scheme for identifying failing vectors in a scan-BIST environment

We present a new scan-BIST approach for determining failing vectors for fault diagnosis. This approach is based on the application of overlapping intervals of test vectors to the circuit under test. Two MISRs (multiple-input signature registers) are used in an interleaved fashion to generate intermediate signatures, thereby obviating the need for multiple test sessions. The knowledge of failing and non-failing intervals is used to obtain a set S of candidate failing vectors that includes all the actual (true) failing vectors. We present analytical results to determine an appropriate interval length and the degree of overlap, an upper bound on the size of S, and a lower bound on the number of true failing vectors; the latter depends only on the knowledge of failing and non-failing intervals. Finally, we describe two pruning procedures that allow us to reduce the size of S, while retaining most true failing vectors in S. We present experimental results for the ISCAS 89 benchmark circuits to demonstrate the effectiveness of the proposed scan-BIST diagnosis approach.

[1]  Tracy Larrabee,et al.  Creating small fault dictionaries [logic circuit fault diagnosis] , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Dong Sam Ha,et al.  AN EFFICIENT, FORWARD FAULT SIMULATION ALGORITHM BASED ON THE PARALLEL PATTERN SINGLE FAULT PROPAGAT , 1991, 1991, Proceedings. International Test Conference.

[3]  Alex Orailoglu,et al.  Improved fault diagnosis in scan-based BIST via superposition , 2000, Proceedings 37th Design Automation Conference.

[4]  Vinod K. Agarwal,et al.  A diagnosis method using pseudo-random vectors without intermediate signatures , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  Saman Adham,et al.  BIST fault diagnosis in scan-based VLSI environments , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[6]  Mark G. Karpovsky,et al.  Design of Self-Diagnostic Boards by Multiple Signature Analysis , 1993, IEEE Trans. Computers.

[7]  T. Larrabee Creating Small Fault Dictionaries , 1998 .

[8]  Peilin Song,et al.  S/390 G5 CMOS microprocessor diagnostics , 1999, IBM J. Res. Dev..

[9]  Charles E. Stroud,et al.  Multiple error detection and identification via signature analysis , 1995, J. Electron. Test..

[10]  Paul H. Bardell,et al.  Self-Testing of Multichip Logic Modules , 1982, International Test Conference.

[11]  Irith Pomeranz,et al.  On Dictionary-Based Fault Location in Digital Logic Circuits , 1997, IEEE Trans. Computers.

[12]  Yuejian Wu,et al.  Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST , 1995, IEEE Trans. Computers.

[13]  Alex Orailoglu,et al.  Diagnosis for scan-based BIST: reaching deep into the signatures , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[14]  Jacob Savir,et al.  Identification of failing tests with cycling registers , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[15]  J. G-Dastidar Fault diagnosis in scan-based bist using both time and space information , 1999 .

[16]  Janusz Rajski,et al.  Fault diagnosis in scan-based BIST , 1997, Proceedings International Test Conference 1997.