Electrothermal coupling analysis of CMOS gates driving interconnects

This paper presents an analytical electrothermal model for transient thermal analysis of interconnects in highspeed integrated circuits. Firstly, a correspondent transmission line network is established based on the structure of the interconnect system, and then moment matching technique is adopted to simplify the expression of the input impedance. Finally, the thermal responses of an interconnect line excited by a periodic rectangular signal are obtained. The proposed model includes the electrothermal effects that the positive feedback occurs between the electrical and thermal behaviors of interconnects. It is shown that the temperature and the propagation delay of interconnects will increase a lot due to the electrothermal coupling effects, especially for interconnects in high-speed integrated circuits.

[1]  Junfa Mao,et al.  Modeling and analysis of electrothermal effects on global ULSI interconnects , 2010, 2010 IEEE Electrical Design of Advanced Package & Systems Symposium.

[2]  Jun-Fa Mao,et al.  Dynamic Power Model of CMOS Gates Driving Transmission Lines Based on Fourier Analysis , 2008, IEEE Transactions on Electron Devices.

[3]  Kaustav Banerjee,et al.  Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[4]  W. Dally.  Interconnect-limited VLSI architecture , 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

[5]  K. Banerjee,et al.  Scaling analysis of multilevel interconnect temperatures for high-performance ICs , 2005, IEEE Transactions on Electron Devices.

[6]  C. Leroux,et al.  Investigations on the thermal behavior of interconnects under ESD transients using a simplified thermal RC network , 1998, Electrical Overstress/ Electrostatic Discharge Symposium Proceedings. 1998 (Cat. No.98TH8347).

[7]  K. Banerjee,et al.  Global (interconnect) warming , 2001 .

[8]  Qing Huo Liu,et al.  Transient Electrothermal Analysis of Multilevel Interconnects in the Presence of ESD Pulses Using the Nonlinear Time-Domain Finite-Element Method , 2009, IEEE Transactions on Electromagnetic Compatibility.

[9]  P. Heydari,et al.  Interconnect energy dissipation in high-speed ULSI circuits , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[10]  C. Hu,et al.  Characterization of VLSI circuit interconnect heating and failure under ESD conditions , 1996, Proceedings of International Reliability Physics Symposium.