EEPROM memory has floating gate with source line selection transistor

The invention relates to non-volatile memory EEPROM electrically erasable and re-programmable, floating-gate transistors. We realized the need to provide in series with each floating gate transistor transistor selection that eliminates leakage currents of the floating gate transistors, leakage currents that may be important after an erase operation of a memory point because positive charges that can be stored on the floating gate. But the selection transistor is bulky. The invention proposes to limit leakage current not by a selection transistor in each memory point but by a comprehensive selection transistor to a line. This TSL1 transistor TSL2 connects to ground a single line of sources both SC1, SC2, that of the transistor line selected for programming. The selection transistor is in fact controlled by the same word line as the floating gate transistors of the same line.