A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%

The present methodology of clock distribution inside high-performance central processing unit chip offers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to Ldi/dt. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current profile (current versus time), by controlling the current on all the complementary metal oxide semiconductor gates of the clock generation circuits. In our methodology, the time for the chip to reach the maximum saturation current is same when compared with the present linear current ramp methodology. We have also developed a new “optimizer program” to show the existence of a unique single current profile solution, which is different from the present methodology. The proposed method requires understanding of how the minimum value of the power supply voltage (supposed to be always 1V for the device) gets changed, when various gates in a clock tree are turned ON at different times (Tn, parameters of the problem) with different values of current (In, other parameters of the problem). Basically, an ensemble of “n” number of transistors will be turned ON at time t=Tn while it will pump the total current I=In. This understanding generates the derivative function of the minimum noise point with respect to these said parameters, which in turn generates a new set of parameters to optimize the noise point. We have found that this optimizer program works and also converges for the generation of minimum power and ground noise, which is 40% lesser than the conventional approach.

[1]  T. Kavitha,et al.  Generalization of clock gating logic using wide spread adapting technique , 2015, 2015 2nd International Conference on Electronics and Communication Systems (ICECS).

[2]  B.K. Bhattacharyya,et al.  A Mathematical Technique to estimate the High Frequency Current Inside the Silicon Die from the Noise Measurements , 2007, 2007 International Conference on Thermal, Mechanical and Multi-Physics Simulation Experiments in Microelectronics and Micro-Systems. EuroSime 2007.

[3]  Yiran Chen,et al.  DCG: deterministic clock-gating for low-power microprocessor design , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Davide De Caro,et al.  New clock-gating techniques for low-power flip-flops , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[5]  Antonio G. M. Strollo,et al.  Low-power flip-flops with reliable clock gating , 2001 .

[6]  Enrico Macii,et al.  Power-aware clock tree planning , 2004, ISPD '04.

[7]  T. Sudo,et al.  Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP , 2012, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).

[8]  Bidyut K. Bhattacharyya,et al.  Reduction of Noise Using Continuously Changing Variable Clock and Clock Gating for IC Chips , 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[9]  Aaron P. Hurst.  Automatic synthesis of clock gating logic with controlled netlist perturbation , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[10]  Shivendra Singh,et al.  Power Optimization of Sequential Circuit Based ALU Using Gated Clock & Pulse Enable Logic , 2014, 2014 International Conference on Computational Intelligence and Communication Networks.

[11]  Kaushik Roy,et al.  Improved clock-gating control scheme for transparent pipeline , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[12]  Daniel Friedman,et al.  A DPLL-based per core variable frequency clock generator for an eight-core POWER7™ microprocessor , 2010, 2010 Symposium on VLSI Circuits.

[13]  Magdy Bayoumi,et al.  Novel clock gating techniques for low power flip-flops and its applications , 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

[14]  Alak Majumder,et al.  LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder , 2016, 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS).

[15]  B. Flachs,et al.  A method to measure impedance of chip/package/board power supply system using pseudo-impulse current , 2006, 2006 IEEE Electrical Performane of Electronic Packaging.

[16]  Harish M. Kittur,et al.  Design and Analysis of Clock Gating Elements , 2016 .

[17]  K. Aygun,et al.  Measurement-to-modeling correlation of the power delivery network impedance of a microprocessor system , 2004, Electrical Performance of Electronic Packaging - 2004.

[18]  Luca Benini,et al.  Clock-tree power optimization based on RTL clock-gating , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[19]  Debasis Baral,et al.  Method to Simulate Rise Time of Current Drawn by a Microprocessor , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[20]  A. Waizman.  CPU power supply impedance profile measurement using FFT and clock gating , 2003, Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).

[21]  Alak Majumder,et al.  A 90 nm leakage control transistor based clock gating for low power flip flop applications , 2016, 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS).

[22]  F.C. Lee,et al.  Adaptive voltage position design for voltage regulators , 2004, Nineteenth Annual IEEE Applied Power Electronics Conference and Exposition, 2004. APEC '04..

[23]  Yici Cai,et al.  An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Gang Huo,et al.  A semi-empirical approach to determine the effective minimum current pulse width (T) for an operating silicon chip , 2007, 2007 International Power Engineering Conference (IPEC 2007).