Application of the self‐aligned titanium silicide process to very large‐scale integrated n‐metal‐oxide‐semiconductor and complementary metal‐oxide‐semiconductor technologies

This paper reviews recent progress towards integrating the self‐aligned titanium silicide process into VLSI NMOS and CMOS technologies, to simultaneously reduce the gate and junction sheet resistances to below 1 Ω/sq. In addition to reviewing the base line self‐aligned TiSi2 process, the key issues that must be addressed if the process is going to be successfully integrated into a VLSI process flow, without having adverse effects on device parameters, will be discussed. Such issues are how the sheet resistance can be reduced to <1 Ω/sq without bridging between the gate and source/drain regions, the effect of silicide stress on gate oxide integrity, and how both P‐ and N‐type junctions can be silicided without adversely affecting diode or transistor properties. Recent results on the hot electron hardness of silicided devices compared to unsilicided transistors will also be presented. The implementation of the self‐aligned titanium silicide process using rapid thermal processing to simultaneously fabricate ...