Static and low frequency noise characterization in surface- and buried-mode 0.1 μm PMOSFETS

Abstract In this work, static and low frequency noise parameter extraction are carried out on surface- and buried-mode 0.1 μm PMOSFETs. The two architectures are based either on a surface mode of operation (SC) or on a buried one (BC) featuring P+ and N+ polygate, respectively. The impact of the gate architecture i.e. P+ and N+ polysilicon, on the static and noise parameters is analyzed. The 1/f noise, which can be interpreted in terms of carrier number fluctuations, is found to be about one decade lower for buried-mode devices. The statistical sample-to-sample dispersion of the noise level has also been studied and found to be as large as 4–5 decades for the nominal area devices. Standard RTS analysis has also been performed on representative PMOS devices.