This paper presents a modified digital background calibration technique to compensate for higher order nonlinearities in a pipelined ADC. The proposed technique uses multiple dithers in a correlation-based background calibration scheme to estimate and compensate higher order nonlinearities. Benefits of this new method in terms of convergence rate and digital complexity over previous work are discussed. Another significant advantage of this scheme is that the convergence of the estimated parameters does not depend on the statistics of the input signal. That makes the calibration effective for any input signal. The proposed technique is implemented in a 12-bit pipelined ADC using the same architecture as in (Keane et al., 2005) for comparison. After calibration, the simulation shows signal to noise ratio of 72 dB and converge after 2 times 108 samples.
[1]
Un-Ku Moon,et al.
Background calibration techniques for multistage pipelined ADCs with digital redundancy
,
2003,
IEEE Trans. Circuits Syst. II Express Briefs.
[2]
B. Murmann,et al.
A 12 b 75 MS/s pipelined ADC using open-loop residue amplification
,
2003,
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[3]
Dong Wang,et al.
Background interstage gain calibration technique for pipelined ADCs
,
2005,
IEEE Transactions on Circuits and Systems I: Regular Papers.
[4]
Ian Galton,et al.
Digital Background Correction of Harmonic Distortion in Pipelined ADCs
,
2006,
IEEE Transactions on Circuits and Systems I: Regular Papers.