A 1.2 GSample/s Double-Switching CMOS THA With ${- }$62 dB THD

Hold-mode feed-through is an important design problem, which plagues the classical switched-buffer track-and-hold amplifier (THA) topologies. The cross-coupled capacitor technique is a simple way of reducing hold-mode feed-through. However, the reduction in hold-mode feed-through is dependent on the matching between the cross-coupled capacitors and the inherent feed-forward capacitors. A double-switching switched-buffer THA is proposed, which has a switching input buffer. The proposed technique results in exceptional hold-mode isolation without the usage of the cross-coupled capacitor technique. Under Nyquist-rate sampling, 62 dB spurious-free-dynamic-range (SFDR), and 10 bit accuracy are achieved with input frequencies up to 800 MHz and 600 MHz respectively. Two prototype chips are designed in a 0.18 mum CMOS process. To maximize speed and dynamic range, the THA makes use of both 3.3 and 1.8 V devices, and uses 3.3 V analog supply voltage. Where necessary, 3.3 V devices cascode the 1.8 V devices for safe operation. The performance of the THA is comparable to most bipolar designs, both in speed and accuracy.

[1]  A. Boni,et al.  A 10-b 185-MS/s track-and-hold in 0.35-/spl mu/m CMOS , 2001 .

[2]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[3]  C.A.T. Salama,et al.  An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology , 2004, IEEE Journal of Solid-State Circuits.

[4]  Yuriy Greshishchev,et al.  A 24GS/s 6b ADC in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  U. Langmann,et al.  A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC , 1997 .

[6]  Robert M. R. Neff,et al.  A 4 Gsample/s 8b ADC in 0.35 μm CMOS , 2002 .

[7]  M.-C.F. Chang,et al.  A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging , 2005, IEEE Journal of Solid-State Circuits.

[8]  M. Flynn,et al.  400 MSample/s 6 b CMOS folding and interpolating ADC , 1998 .

[9]  Behzad Razavi.  Design of sample-and-hold amplifiers for high-speed low-voltage A/D converters , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[10]  W. Sansen,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[11]  Jingbo Wang,et al.  A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture , 2006, IEEE Journal of Solid-State Circuits.

[12]  Asad A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS , 2001 .

[13]  A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[14]  M. Waltari,et al.  A 10-bit 220-MSample/s CMOS sample-and-hold circuit , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[15]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[16]  U. Langmann,et al.  A 1.2-GS/s 8-b silicon bipolar track & hold IC , 1996 .

[17]  R. Roovers,et al.  A 12 b 50 M sample/s cascaded folding and interpolating ADC , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[18]  A. Montijo,et al.  A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[19]  Mau-Chung Frank Chang,et al.  A 10-b, 1-GSample/s track-and-hold amplifier using SiGe BiCMOS technology , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[20]  C. Fiocchi,et al.  A 10 b 250 MHz BiCMOS track and hold , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[21]  Piet Wambacq,et al.  Distortion analysis of analog integrated circuits , 1998 .

[22]  Shouli Yan,et al.  A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 µm CMOS , 2009, IEEE J. Solid State Circuits.

[23]  Lawrence E. Larson,et al.  A broadband 10-GHz track-and-hold in Si/SiGe HBT technology , 2001 .

[24]  J. Jacob Wikner,et al.  CMOS Data Converters for Communications , 2000 .

[25]  Raf Roovers,et al.  12-B, 60-MSample/S cascaded folding and interpolating ADC , 1999 .

[26]  M. Flynn,et al.  A 400 M sample/s 6b CMOS folding and interpolating ADC , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[27]  A. N. Karanicolas.  A 2.7-V 300-MS/s track-and-hold amplifier , 1997 .

[28]  B. Streetman.  Solid state electronic devices , 1972 .

[29]  P. Vorenkamp,et al.  Fully bipolar, 120-Msample/s 10-b track-and-hold circuit , 1992 .

[30]  Shouli Yan,et al.  A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[31]  Ying-Hsi Lin,et al.  An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[32]  Bram Nauta,et al.  A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[33]  R.C. Taft,et al.  A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency , 2004, IEEE Journal of Solid-State Circuits.