A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces

A 6 b 10-tap digital FIR filter has a self-timed datapath, clocked interfaces, and variable latency. The architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. The 0.45 mm/sup 2/ circuit, in 0.18 μm CMOS technology, is operational from 1.2 V to 2.1 V power supply, and has 80 mW dissipation at 300 MSample/s and 4 cycles of latency, and 500 mW at 1.3 GSample/s and 7 cycles of latency.

[1]  Scott K. Reynolds,et al.  Digital FIR filters for high speed PRML disk read channels , 1995 .

[2]  A. Rylyakov,et al.  A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[3]  Steven M. Nowick,et al.  Fine-grain pipelined asynchronous adders for high-speed DSP applications , 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.