Sequential circuit design using synthesis and optimization
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Robert K. Brayton | Alberto L. Sangiovanni-Vincentelli | Kanwar Jit Singh | Ellen Sentovich | Hamid Savoj | Cho W. Moon | R. Brayton | A. Sangiovanni-Vincentelli | E. Sentovich | H. Savoj | K. J. Singh | C. Moon
[1] Robert K. Brayton,et al. Delay optimization of combinational logic circuits by clustering and partial collapsing , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[2] Robert K. Brayton,et al. Algorithms for discrete function manipulation , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[3] Robert K. Brayton,et al. Extracting local don't cares for network optimization , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[4] Robert K. Brayton,et al. Retiming and resynthesis: optimizing sequential networks with combinational techniques , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Giovanni De Micheli. Synchronous logic synthesis: algorithms for cycle-time minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Tracy Larrabee. Efficient generation of test patterns using Boolean difference , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[7] Jan M. Rabaey,et al. A VLSI wordprocessing subsystem for a real time large vocabulary continuous speech recognition system , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.
[8] Stephen H. Unger,et al. Minimizing the Number of States in Incompletely Specified Sequential Switching Functions , 1959, IRE Trans. Electron. Comput..
[9] Robert K. Brayton,et al. Performance optimization of pipelined circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[10] Robert K. Brayton,et al. Preserving Don't Care Conditions During Retiming , 1991, VLSI.
[11] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[12] A. Richard Newton,et al. Don't care minimization of multi-level sequential logic networks , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[13] J. Rajski,et al. A method for concurrent decomposition and factorization of Boolean expressions , 1990, ICCAD 1990.
[14] Robert K. Brayton,et al. Timing analysis and delay-fault test generation using path-recursive functions , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[15] Fabio Somenzi,et al. Exact and heuristic algorithms for the minimization of incompletely specified state machines , 1994, Proceedings of the European Conference on Design Automation..
[16] Robert K. Brayton,et al. Computing the initial states of retimed circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[17] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[18] Robert K. Brayton,et al. Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[19] Tiziano Villa,et al. NOVA: State Assignment of Finite State Machines for Optimal Two-Level Logic Implementations , 1989, 26th ACM/IEEE Design Automation Conference.
[20] Robert K. Brayton,et al. Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..