Warpage Study of Large 2.5D IC Chip Module

Large 2.5D IC leads the trend for Field Programmable Gate Array (FPGA), graphic, and network application. Chip module (CM) is comprised of top die and Si interposer, and underfill (UF) is fully filled between them. However, coefficient of thermal expansion (CTE) of UF is greater than 20ppm, and CTE mismatch occurs between UF and Si (CTE~3ppm). How to tune chip module warpage is a key for large 2.5D IC. Chip module size of conventional 2.5D IC is less than 30mm × 30mm, but side length of large 2.5D IC will be longer than 40mm, which causes UF volume is rapidly increasing, so CTE mismatch become more serious than before. In this study, compound structure and UF volume tuning are utilized for reducing chip module warpage. There are two top dies bonded on interposer, and size of top die and interposer is 20mm × 25mm and 40mm × 30mm. For compound structure, molding compound is covered on top die and interposer after UF curing and is capable to balance CTE mismatch from UF. For UF volume tuning, bump height (BH) control of micro bump on top die is implemented to optimize UF volume. In this study, oval micro bump is used and bump diameter is 40um × 70um. 1X and 0.69X BH are implemented. From UF volume study results, when UF volume reduces 31%, the warpage gap between chip module and substrate (SBT) can reduce 10% at room and high temperature. From compound structure study results, the chip module with molding compound successfully declines the effects of CTE mismatch and leads that warpage gap between chip module and substrate is also reduced 87% at high temperature.