Design and Implementation of an Object-Oriented Framework for Dynamic Partial Reconfiguration

Although both DPR (dynamic partial reconfiguration) and HLS (high level synthesis) are important future trends regarding hardware design, they develop quite independently. Today's software-to-hardware compilers focus on conventional hardware and therefore have to remove dynamic aspects such as the instantiation of calculating modules at runtime. On the other hand, DPR tools are working on the lowest possible layer regarding FPGAs: the bitfile level. This paper focuses on the design and the implementation of a Framework combining the two technologies, since this has the potential to kill two birds with one stone. Firstly, DPR can change the programming paradigm in future HDLs regarding dynamic instantiations. Dynamic parts would not have to be removed any longer but could be realized on the target FPGA using DPR. Secondly, a high-level language support of DPR technologies could help end its shadowy existence and turn it into a commonly used method.